1. Field
The embodiments discussed herein are directed to a power circuit and method of power control.
2. Description of the Related Art
Improvements in the capabilities of personal computers (hereinafter referred to as PCs) have become significant and contributed to advances in the information processing community. One of factors responsible for the above-described improvements is the increasing performances of central processing units (CPUs). However, the power consumption and the heating value of the CPUs have also been increasing in recent years causing a problem of how to keep the performances, the power consumption, and the heating value of the CPUs within predetermined bounds.
When a PC performs simple processing, the use of a control system arranged to reduce the power consumption by decreasing the voltage of a power source provided for the CPU has become commonplace. Especially when a mobile PC is used, the control system may be used to increase the battery retaining time.
FIG. 1. As illustrated in FIG. 1, the PC 10 is provided as a mobile PC, and includes a CPU 101, a peripheral large scale integration (LSI) circuit 102 including a chip set or the like, a hard disk device (HDD), various input/output devices 103 including a hard disk device (HDD), a keyboard, etc., a universal serial bus (USB) connector 104a, a local area network (LAN) connector 104b, an external monitor output connector 104c, an external power input unit 105, a charging circuit 106, various power sources 107, and a CPU core power source 110.
The CPU 101 executes various calculation processings. The peripheral LSI circuit 102 controls information exchanged between the internal various input/output devices 103 based on instructions of the CPU 101. Further, the peripheral LSI circuit 102 controls information exchanged between the PC 10 and various USB devices 23, various communication devices 24, and an external monitor 25 via the individual USB connector 104a, LAN connector 104b, and external monitor output connector 104c. 
The external power input unit 105 distributes power supplied from an alternating current (AC) adapter 21 and/or an internal and/or external battery 22 to the charging circuit 106, the various power sources 107, and the CPU core power source 110. The charging circuit 106 controls charging of the battery 22. Each of the various power sources 107 supplies power to each of the components except the CPU 101, so as to drive each of the components except the CPU 101.
The CPU core power source 110 includes a power control unit 111, an oscillation circuit 118, and a smoothing circuit 119, and supplies power used to drive the CPU 101. The oscillation circuit 118 includes an input capacitor and/or a field effect transistor (FET), and generates a clock pulse signal. The smoothing circuit 119 includes a coil and/or an output capacitor, smoothes the clock pulse signal, and supplies the smoothed clock pulse signal to the CPU 101 as power.
The power control unit 111 includes a control signal input unit 112, a digital-to-analog (D/A) converter 113, a reference voltage generating unit 114, an error amplifier unit 115, a pulse width modulation (PWM) generating unit 116, and a driver unit 117, and controls the oscillation circuit 118.
The control signal input unit 112 receives a power voltage control signal transmitted from the CPU 101. The D/A converter 113 converts the power voltage control signal into an analog signal, and the reference voltage generating unit 114 generates a reference voltage based on the power voltage control signal converted into the analog signal. The error amplifier unit 115 compares the reference voltage to a voltage transmitted from the smoothing circuit 119, and transmits data of the difference between the above-described voltages. The PWM generating unit 116 transmits an oscillation control signal subjected to PWM modulation performed based on the magnitude of the data transmitted from the error amplifier unit 115. The driver unit 117 drives the oscillation circuit 118 based on the oscillation control signal.
When PC 10 performs simple processing, interrupt processing may be periodically performed by recovering a voltage so as to control the various devices, for example, even though the voltage of the power source provided for the CPU 101 is reduced to some extent. Since the output capacitor may be provided with many electric charges so as to recover the voltage, a large current periodically occurs in the CPU core power source 110.
Then, when the large current flows into the CPU core power source 110, a distortion occurs in the capacitor and/or the coil due to the occurrence of an electromagnetic field, and the distortion propagates to a print substrate. Therefore, when the voltage is periodically recovered, as illustrated in FIG. 4, the print substrate is periodically vibrated. Then, if the period is an audible frequency, the print substrate functions as a speaker, and the sound of the frequency corresponding to the period is generated from the entire print substrate.
The loudness of the above-described sound (hereinafter referred to as a “ringing sound”) generated due to the vibration of the print substrate is so high that a person can perceive the ringing sound, which is often offensive to the person.
The ringing sound can be reduced to some extent by providing a specifically designed capacitor and/or a specifically designed coil as the above-described capacitor and coil. However, the reduction effect is often definitive and the parts used for the specifically designed capacitor and coil are often expensive. Further, even though the ringing sound can be reduced to some extent by adjusting the part arrangement and/or wiring, the reduction effect may be definitive. Further, being affected by other parts and/or wiring, the know-how to achieve the ringing sound reduction often becomes significantly difficult.
In addressing a ringing sound problem, conventionally a changing an intermittent control performed for the active state and the idle state of a CPU so that the CPU does not perform an intermittent operation at the same intervals as those at which the intermittent control is performed is disclosed.